| 摘要 |
The vertical synchronization and field detecting circuit comprises a time mask for masking a noise signal for an input composite synchronizing signal, a first counter for counting only an input signal, a third counter for selectively counting an equalizing signal, a fourth counter for counting the number of composite synchronizing signals and vertical synchronizing signals, a second counter for counting the number of vertical synchronizing signals and a field detector for detecting odd- and even-numbered field signals, thereby reducing manufacturing cost.
|
