| 摘要 |
Adder units are used to compare two numbers. A first logic unit receives one or more bits from a first number and the bits from a second number less the least significant bit of that second number. A second logic unit receives one or more bits from the second number and the bits from the first number less the least significant bit of that first number. The logic units generate, based on the logic values (bits) input into the logic units, logic values and output those values to an adder unit. Using these values, in addition to a "Carry In" value, the adder unit generates an output. The output is at least partially determinative of whether the second number is greater than the first number. Comparators designed in accordance with the present invention incur less delay (i.e., are faster) and require less inputs into logic look-up tables than prior comparators.
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