发明名称
摘要 PURPOSE:To attain to enhance reliability and operability, by providing a battery voltage detection circuit and a standing time detection circuit and forcibly setting a mode control circuit to a clock mode by the respective detection signals of both circuits. CONSTITUTION:A depth-of-water meter circuit 17 starts water pressure measuring operation based on the signal from a water pressure sensor 7. Subsequently, a depth-of-water detection circuit 20 detects a depth-of-water information signal P3 and a water quality detection signal PK1 is reversed to a L-level. As a result, a standing time detection circuit 25 brings the reversal signal PK1 to a H-level through an inverter 66 to be reset again. When the operation time of the circuit 25 is elapsed, a time-up signal PZ is outputted from the circuit 25 to reset a mode control circuit 39 through an OR gate 68. As a result, the circuit 39 is forcibly set to the setting state of an output terminal Q1 to output a clock function setting signal PC1 and returned to a clock mode. When the voltage of a radio wave BT is lowered, a battery voltage detection circuit 48 detects voltage drop to output a voltage drop detection signal PBD and resets the circuit 39 through the gate 68.
申请公布号 JPH0664162(B2) 申请公布日期 1994.08.22
申请号 JP19850250332 申请日期 1985.11.08
申请人 发明人
分类号 G01C13/00;G04G21/00;G04G99/00 主分类号 G01C13/00
代理机构 代理人
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