| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which reduces generation of multi-bit errors. SOLUTION: In the semiconductor memory device, four access transistors N3A, N4A, N3B, and N4B of two adjacent memory cells MC0 and MC1 in the same row are formed in a common p-type well 3. Each gate of the access transistors N3A and N4A of the memory cell MC0, and each gate of the access transistors N3B and N4B of the memory cell MC1 are electrically connected with different word lines WLA and WLB, respectively. COPYRIGHT: (C)2008,JPO&INPIT
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