发明名称
摘要 <p>A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geometrical layout design data extracted from one or more data-format files into each of a structural data, a spatial data, and a raw-geometry data. Thereafter, one or more predefined operations are performed on one or more of the structural data, the spatial data, and the raw-geometry data.</p>
申请公布号 JP2009516876(A) 申请公布日期 2009.04.23
申请号 JP20080540791 申请日期 2006.11.10
申请人 发明人
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址