CLOCK OSCILLATOR AND METHOD OF OPERATION

摘要

PURPOSE: To provide the clock oscillator and operating method. CONSTITUTION: The clock oscillator 10 has an enable circuit 16, a burst counter circuit 14, and an oscillation circuit 12. This enable circuit 16 generates a specific 1st signal in response to an input state. The burst counter circuit 14 receives a clocking signal and generates a specific 2nd signal in response to a specific number of oscillations of the clocking signal. The oscillation circuit 12 is coupled with the enable circuit 16 and burst counter circuit 14. The oscillation circuit 12 generates a clock signal as its output in response to the specific 1st signal and generates a constant logical state as its output in response to the specific 2nd signal. The clock oscillator 10 is used suitably by a system when a low reference clock signal is predicted or if a large acquisition penalty is generated eventually owing to frequent variation in reference clock frequency. This clock oscillator can be held so that a phase lock is matched with frequency variation of the input reference clock signal.