| 摘要 |
1,256,950. Transistor pulse circuits. RCA CORPORATION. 10 Sept., 1969 [17 Sept., 1968], No. 44760/69. Heading H3T. [Also in Division G4] A divider consists of two invertors such as F.E.T.'s 12, 22, a first gate or switch 40 such as F.E.T.'s 42, 44 connecting the output of F.E.T. 12 to the input of F.E.T. 22 and a second gate or switch 30 such as F.E.T.'s 32, 34 connecting the two inputs of F.E.T.'s 12, 22; the input and output voltages being stored during changeover on CA, CB. The switches are enabled alternately. The F.E.T.'s 42, 44 are parallel connected complementary types and are controlled respectively by the clock pulses CP and their complement CP, so that they turn on and off together and eliminate any threshold voltage drop which would arise if only one were used, operating in source follower mode. Similarly, F.E.T.'s 32, 34 operate together, but they are out of phase with F.E.T.'s 42, 44. Preferably the drains of F.E.T.'s 12, 22 a re connected through further F.E.T.'s 14, 24 to the positive supply, 50. When gate 40 is opened by a positive clock pulse CP (and a negative CP), the gate and output line CP1 capacitances C A are charged to the positive supply voltage through F.E.T. 14 provided the voltage on the gate capacitance of F.E.T. 12, C B , is zero. When the clock pulse changes level (Fig. 2, not shown) gate 40 closes and gate 30 opens so that C B is charged from C A , the latter being larger than C B so that its voltage does not drop too much during charging of C A . When the next clock pulse occurs and C P is positive, F.E.T. 12 being turned on by the positive charge on its gate, and its drain thus dropping towards zero, this zero level is transmitted through gate 40 to F.E.T. 22 which is turned off. Thus a square wave CP1 appears at the output having half the frequency of the clock pulses. In an alternative form (Fig. 3, not shown), the drains of F.E.T.'s 14, 15 are connected individually to the corresponding source electrodes of the F.E.T.'s (42a, 44a) in the first gate (40a). |
