| 摘要 |
The generator receives a series of timing pulses which are fed into a multiple delay system consisting of a delay line with several tappings, producing a number of signals of different phases. These signals are fed into a selector circuit. The circuit also receives data from an up-down counter. The output of the selector circuit is fed to a flip-flop which halves the input frequency, and consists of a J-K flip-flop. Its output is connected to the D terminal of a D- flip-flop which is fed with a timing signal, and its outputs are connected to a number of AND-gates.
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