发明名称 |
Memory test circuit |
摘要 |
A memory test circuit in which test data is simultaneously written into plural memory cells of a semiconductor memory device and then subsequently read from the plural memory cells to assure reliable operation of the memory device. A logical sum and a logical product are formed of the test data read out from the plural memory cells. The logical product and the logical sum are subjected to an exclusive-or operation, the result of which is indicative of whether or not the test data was correctly written into the memory cells.
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申请公布号 |
US4686456(A) |
申请公布日期 |
1987.08.11 |
申请号 |
US19860846143 |
申请日期 |
1986.03.31 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
FURUYAMA, TOHRU;OHSAWA, TAKASHI |
分类号 |
G01R31/26;G11C29/08;G11C29/26;G11C29/34;G11C29/38;(IPC1-7):G01R31/26;G11C29/00 |
主分类号 |
G01R31/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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