| 摘要 |
A high resolution pipelined digital-to-analog converter is disclosed having at least one switching circuit for conveying charge to at least one conversion capacitor upon receipt of a digital signal during the first half of a clock cycle. Additional switching circuits are provided for transferring the charge from the conversion capacitors to a feedback capacitor during the second half of the clock cycle. Also provided is a circuit for discharging an analog output from, and preventing the charging of, the feedback capacitor during the first half of a succeeding clock cycle. In a preferred embodiment, the pipelined digital-to-analog converter comprises a first plurality of electrical circuits having at least one feedback capacitor and a plurality of conversion capacitors adapted for accepting digital and analog inputs, wherein the ratio of the feedback capacitance to each of the conversion capacitances is substantially independent of the resolution of the converter. A second plurality of electrical circuits is also provided which is operable to delay at least one bit of the digital signal to one of the first plurality of electrical circuits. The digital-to-analog converter is operable to allow the number of n-bit digital words converted by the converter to be independent of the resolution of the converter. |
