发明名称 |
Semiconductor memory using select transistors coupled to sub-bitlines from different blocks |
摘要 |
The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.
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申请公布号 |
US5852570(A) |
申请公布日期 |
1998.12.22 |
申请号 |
US19970866498 |
申请日期 |
1997.05.30 |
申请人 |
SHARP KABUSHIKI KAISHA |
发明人 |
HOTTA, YASUHIRO;NOJIMA, TAKESHI;KOMATSU, KOJI |
分类号 |
G11C17/00;G11C16/04;G11C16/06;G11C17/12;H01L21/8246;H01L27/10;H01L27/112;(IPC1-7):G11C17/00 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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