| 摘要 |
PROBLEM TO BE SOLVED: To reduce high frequency noises produced in a control circuit which controls a power supplied to a load. SOLUTION: A pulse width modulator has a quasi-random number generator and introduces a quasi-random offset delay 605 into an active high pulse 607. Digital pulses from a delta-sigma modulation circuit in a pre-stage are integrated by a pulse counter to find duty cycles in respective modulation period. If the duty cycle exceeds 50% (period 2), a protocol in that period in inverted by a protocol inverter. In the diagram, the protocol in the period 2 is lower active 609. Like this example, if an immediately prior period (period 1) has a different protocol (high active from the protocol (low active) of the present period (period 2), an offset delay 611 is made to be zero. With this constitution, the signal level of the present period is aligned with the signal level of the immediately prior period as shown by a waveform 615, so that the number of transitions can be reduced. |
