| 摘要 |
PURPOSE: To provide a circuit of low input capacitance, capable of driving a large capacitance load by arranging a CMOS logic stage in plural signal lines from an input terminal to a push-pull stage and controlling propagation delay in the signal lines, so as to be almost equal to each other. CONSTITUTION: Input signals D are transmitted through the parallel signal lines 10, 20 and 30. Transistors(TRs) P1 and N1 control a BICMOS pull-up circuit for output Q' and the TRs P6 and N6 control a pull-down driver for the output Q. The TRs P2 and N2 invert the input signals and supply the inverted signals to the pull-up circuit 27 for the output Q and the pull-down driver 25 for the output Q'. In the constitution, by making all the ratios of the dimensions of the P1 and the N1, the P2 and the N2 and the P6 and the N6 the same and turning input inverters 11, 12 and 21 to the appropriate dimension, without changing the designs with respect to other elements, low-speed and high-speed signal lines are set and respective total propagation delay amounts are made almost equal. |
