发明名称 Integrated circuit comprising conductive lines with negative profile and related method of fabrication
摘要 <p>A semiconductor integrated circuit comprising lines of conductive material (4) for the electrical interconnection between parts of the circuit, and a layer of dielectric material (6), superimposed to the lines of conductive material (4). The lines of conductive material (4) have a vertical profile such that the smallest distance between two adjacent lines of conductive material is located at their upper surfaces. <IMAGE></p>
申请公布号 EP0978875(A1) 申请公布日期 2000.02.09
申请号 EP19980830489 申请日期 1998.08.07
申请人 STMICROELECTRONICS S.R.L. 发明人 BACCHETTA, MAURIZIO;VASSALLI, OMAR;ZANOTTI, LUCA
分类号 H01L23/522;H01L23/528;(IPC1-7):H01L23/522 主分类号 H01L23/522
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