发明名称 COMPUTER SYSTEM AND METHOD OF MAINTAINING CONSISTENCE OF MEMORY IN A NON-BLOCKING STREAM QUEUE OF BUS ACCESS REQUESTS
摘要 A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
申请公布号 PL178832(B1) 申请公布日期 2000.06.30
申请号 PL19950307473 申请日期 1995.02.28
申请人 INTEL CORP. 发明人 BRAYTON JAMES M.;RHODEHAMEL MICHAEL W.;SARANGDHAR NITIN V.;HINTON GLENN J.
分类号 G06F9/38;G06F12/08;G06F13/18 主分类号 G06F9/38
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