发明名称 |
MONOS flash memory for multi-level logic and method thereof |
摘要 |
The present invention provides a structure and method of manufacturing split gate MONOS multi-level logic memory device. The memory device has a poly stacked gate transistor 20A in series with a MONOS transistor 24A. The device has a novel operation to achieve multi-level memory storage (e.g., 4 voltage states). The method begins by forming a tunnel oxide layer 30 on the surface of a semiconductor substrate 10. The substrate having a stacked gate channel area 20 and a MONOS channel area 24 in the active regions. A poly floating gate electrode 32 is formed over the stacked gate channel region 20. A ONO layer having a memory nitride layer is formed over the floating gate 32 and the tunnel oxide layer over the MONOS channel region 24. A control gate electrode 44 is formed over the ONO layer 41 spanning across the poly floating gate electrode 32 and the MONOS channel region 24. Source/drain regions 50 51 are formed in the substrate. A poly flash transistor 20A and a MONOS flash transistor 24A combine to form the 4 level logic memory cell of the invention.
|
申请公布号 |
US6166410(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19980166390 |
申请日期 |
1998.10.05 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
LIN, RUEI-LING;HSU, CHING-HSIANG;LIANG, MONG-SONG |
分类号 |
G11C11/56;H01L21/28;H01L21/8246;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L27/148 |
主分类号 |
G11C11/56 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|