发明名称
摘要 A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein the first wiring formation step comprises forming a first trench for a first embedded wiring in a first insulating layer disposed on a substrate and embedding in the first trench, in turn, a first conductive layer and a first conductive capping layer; the first connecting portion formation step comprises forming a second insulating layer on the first insulating layer and the first conductive capping layer, forming a via-hole in a part of the second insulating layer at the first conductive capping layer, and embedding a conductive connecting portion in the via-hole and connected to the first conductive layer; and the second formation step comprises forming a third insulating layer on the second insulating layer and the conductive connecting portion, forming a second trench for a second wiring in the third insulating layer at the conductive connecting portion, and embedding a second conductive layer in the second trench and connected to the conductive connecting portion.
申请公布号 JP3304754(B2) 申请公布日期 2002.07.22
申请号 JP19960089507 申请日期 1996.04.11
申请人 发明人
分类号 H01L21/3205;H01L23/52;H01L23/532;H01L23/538;(IPC1-7):H01L21/320 主分类号 H01L21/3205
代理机构 代理人
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