发明名称 PAY SCRAMBLE DECODER
摘要 PURPOSE:To simplify a connecting part by capturing the absolute minimum data amounts outputted from a descramble module, to obtain the freedom degree of connectability with an outside CPU even when specification change occurs, and to improve flexibility. CONSTITUTION:Scramble related information included in demodulated data from a tuner and demodulating part 100 is processed by a packet extracting and processing part 2 of a descramble module 200, and decoded by a security logic circuit 3. A signal for voice release after decoding is applied to a data decoding part 8, and a signal for video release is inputted to a video signal processing circuit 5. Scramble related display data from the packet extracting and processing part 2 or the data on operation from the security logic circuit 3 are inputted to a buffer control part 30. The buffer control part 30 outputs necessary display data in response to a CPU 101 of the tuner and demodulating part 100. Thus, the absolute minimum communication can be realized, and communication with an outside can be attained.
申请公布号 JPH06338875(A) 申请公布日期 1994.12.06
申请号 JP19930125814 申请日期 1993.05.27
申请人 TOSHIBA CORP 发明人 OKITSU YUKINOBU;NISHIURA MASAAKI
分类号 H04K1/00;H04L9/06;H04L9/10;H04L9/14;H04N7/16;H04N7/20;(IPC1-7):H04K1/00 主分类号 H04K1/00
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