| 摘要 |
PROBLEM TO BE SOLVED: To facilitate measurement of EMI characteristics of a chip on which a clock generation circuit is mounted.SOLUTION: A clock generation circuit includes: a PLL circuit including a first frequency divider and constituted so as to generate a first clock by multiplying a reference clock supplied from the external so that a phase of a feedback clock is synchronized with a phase of the reference clock and generate a feedback clock by causing the first frequency divider to divide the first clock by a first frequency division ratio; and a second frequency divider for generating a second clock by dividing the first clock by a predetermined frequency division ratio. The second frequency divider is a clock generation circuit to be actuated so as to divide the first clock by the first frequency division ratio and then divide the first clock by a second frequency division ratio different from the first frequency division ratio.SELECTED DRAWING: Figure 2 |
