发明名称 Verfahren und Schaltungsanordnungen zur Synchronlaufkontrolle bei der UEbertragung digitaler Nachrichten
摘要 1,190,904. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 13 Jan., 1969 [16 Jan., 1968], No. 1924/69. Heading H4P. A receiver, fed by a digital signal comprising blocks of d data bits separated by s synchronizing bits, is synchronized by circuitry comprising a comparator, which compares groups of the received signals with locally generated sync. bits, and a counter which is incremented or decremented depending upon the comparator output. In the embodiment described the received signal is in ciphered form. The signal and a key signal are fed to a signal register and a key register, respectively, each of capacity s-bits, the registers' serial outputs being modulo-2 added to provide the clear text. The parallel outputs of the registers pass to a comparator in which corresponding bits are modulo-2 added, a counter giving an output if the number of unlike bits in the compared synchronized sequences is less than, for example, 3. At the end of each cycle of d + s clock pulses the counter output is sampled. If there are less than 3 inequalities, resulting in a " positive " comparison, a second counter having a maximum count of 8 is incremented by one unless the counter is already at count 8. The counter is decremented if there are more than 2 inequalities. Should the counter reach zero loss of sync. is assumed and a resynchronization process takes place. In this process the key signal generator and register are stepped forward very rapidly by 4(d + s) steps and are held in the position attained while comparison is made, at received bit rate, between the contents of the key register and the words successively appearing in the signal register. If no positive comparison occurs during a period of 8(d + s) received bits the key generator and register are stepped rapidly by 8(d + s) steps, and further comparison takes place over a period of 8(d + s) bits. This cycle repeats until a positive comparison occurs, whereupon the second counter is incremented and the resynchronization process stops, it being re-initiated if the counter reverts to zero.
申请公布号 DE1815233(A1) 申请公布日期 1969.08.14
申请号 DE19681815233 申请日期 1968.12.17
申请人 INTERNATIONAL BUSINESS MACHINES CORP. 发明人 SENIZERGNES,ANDRE
分类号 H04L7/04;H04L7/08;H04L9/00;H04L9/12 主分类号 H04L7/04
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