| 摘要 |
1,255,206. Transistor bi-stable circuits. MOTOROLA Inc. 29 April, 1969 [13 May, 1968], No. 21758/69. Heading H3T. [Also in Division G4] Cross-coupled transistors 28, 30 forming a bistable memory circuit 25, each have first input terminals such as emitters 34, 38 connected to a common word select line 32, and second input terminals such as further emitters 36, 40 connected to respective sense/write lines 20, 22, and a circuit 27 using for example transistors 60, 62 senses identity of logic state between the bi-stable and the write circuitry connected to lines 20, 22. For reading or writing, the word select line 32 is raised to + 3V BE , and the state of the bi-stable is read by whichever of the emitters 36, 40 conducts into its sense/write line, and is set by appropriately biasing the lines 20, 22 by means of the write circuitry. To detect identity between the bi-stable state and the write circuitry state by the so-called process of association, the word select line is held at a lower potential of 1V BE . Supposing a bi-stable "1" to be T28 ON and T30 OFF, and a write circuitry "1" to be line 22 at 1V BE and line 20 at 3V BE , then neither of the transistors 60, 62 conducts and identity is indicated thereby. If the bistable is "0" however, T30 is ON and T60 emitter voltage is V BE +V CE(SAT) (at T30 collector) plus the small voltage across resistor 52, and its base voltage being 3V BE causes T60 to turn ON. This indicates lack of identity, and a sense amplifier 16 supplies this current flow at terminal 13 to the output 18. In an array of similar memory circuits any one circuit whose stored information is not of immediate interest may be masked or inhibited by holding both sense/ write lines at a certain potential, thereby forcing the memory circuit to indicate association. |
