| 摘要 |
A 12-bit word, including a polarity of sign bit Qs and up to seven initial zeroes preceding a group of significant bits, is converted into a compressed eight-bit word which retains the sign bit Qs in first position and four significant bits X, Y, Z, W in the last positions; the intervening three bits are the binary equivalent of the number of initial zeroes. These intervening bits are generated by a three-stage reverse counter which is loaded by a starting pulse after arrival of the sign bit and is stepped by successive clock pulses, stopping after seven cycles at the count 0 unless cut off earlier by the arrival of the first "one" following the sign bit in the original word. This first "one", or a timing pulse occurring seven cycles after the starting pulse, initiates the stepping of a shift register in which the bits X, Y, Z, W are entered for subsequent transfer to a synthesizing register also receiving the sign bit Qs and the reading of the reverse counter. |
