| 摘要 |
PURPOSE:To reduce the quantity of jittercaused by a data pattern without using differentiating and rectifying circuits, and to improve the purity of data regeneration and reference carrier wave regeneration by regenerating a clock from an output after an orthogonal synchronization detection of a modulated receiving wave. CONSTITUTION:An MSK modulated receiving wave is inputted to FFs 44-47, an output of a 0, pi/4, pi/2, 3pi/4 phase shifter 48 which inputs an output from a VCO40 is inputted to a clock terminal C of the FFs 44-47, and an orthogonal detection is executed by the FFs 44-47. The respective outputs of these FFs 44, 46 and FFs 45, 47 are inputted to EX-ORs 33, 34, a sum component after an orthogonal detection is outputted, an output of the EX-Or 33 is provided to an EX-OR38, and an output of the EX-OR34 is provided to a digital PLL36. Also, an orthogonal detection output of the FFs 44, 46 and an output of the PLL36 are inputted to a data regenerating circuit 35. In this way, a jitter quantity caused by a data pattern is reduced with a simple circuit constitution without using differntiating and rectifying circuits, etc., and the purity of data regeneration and reference carrier wave regeneration is improved. |
