| 摘要 |
A timing pulse generator comprises a flip-flop set by a gate pulse (or a horizontal synchronizing pulse), a NAND gate receiving an inverted gate pulse and an inverted output of the flip-flop, an oscillator controlled by the output from the NAND gate and producing a first clock pulse, a means for producing a second clock pulse in response to the first clock pulse to clock the flip-flop, and a counter counting the first clock pulse and being reset by the output from the flip-flop. |
