| 摘要 |
PURPOSE:To reduce the number of times of timings of a RAS and a CAS for refreshing, by constituting a MOS dynamic RAM so that the refreshing can be performed in a single action by a data input at time of trailing a WE input when a CAS before RAS refresh operation is performed. CONSTITUTION:A data input buffer 10, when a CAS input on a signal line 2 and the WE input on a signal line 1 are inputted, outputs data held by an R/W clock on a signal line 7 onto a signal line 27. A refresh controller 13 outputs a RAS trigger for the number of values of the input data on the signal line 27. When the CAS before RAS refresh operation is performed, by inputting the data input at time of trailing the CAS input and the WE input, and using the valve for the control of the refreshing, the arbitrary number of times of refreshing can be performed in one refresh instruction.
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