| 摘要 |
PURPOSE:To perform a high speed test, by providing an input register, a line register, an output register, an error display register and a test control circuit. CONSTITUTION:An input register 1 has shifting function and parallel storing function and is connected to the input of PLA (Programmable Logic Array) 16 and a line register 2 accesses each line of PLA 16 having shifting function and adding function. An output register 3 has shifting function, adding function and parallel storing function and is connected to the output of PLA 16 and an error display register 4 has adding function for holding a test result and a test control circuit 5 selects and controls the functions of the registers. By this method, the pattern of PLA 16 can be tested on the basis of the reading and adding cumulative cycle of the OR part data of PLA 16 due to the line register 2 and the reading and adding cumulative cycle of the AND part data of PLA 16 due to the input register 1 and the increase in an inspection time accompanied by the increase in the number of the input lines of PLA and the number of lines can be minimized. |
