| 摘要 |
PURPOSE:To improve a processing speed by executing image synthesis processing (logical operation) more than two by means of hardware. CONSTITUTION:For generating video signals A and B, a CPU2 starts a direct memory access (DMA). The started DMA loads an address on a bus 300, accesses bit map memories 31a and 31b, and objective data is outputted to a bus between ALUs 35a and 35b. The data is connected with the ALUs 35a and 35b and logical operation is executed in accordance with instruction registers 34a and 34b. The operated results are respectively outputted to registers 36a and 36b as output signals. The outputs of the registers 36a and 36b are inputted to video signal generation circuits 37a and 37b, and are synchronized with video clock signals, whereby the video signals A and B are generated. Since the image synthesis (logical operation) processings >=2 times are executed by hardware, the processing speed can be improved. |
