摘要 |
In the adder circuit according to the subject of the invention, the basic sum number (0, 4, 8, 12 or 16) is first formed. Then the number 0, 1 or 2, or the numbers 1 and 2, are added to this basic sum number, so that the sum is formed. If this sum is greater than the number 9, it is reduced by the number 10 in circuit 7. A special circuit according to P 3832115.7 is used as the main circuit, and is numbered 5 in Figure 3. Circuit 4 is an additional circuit, using which the number of required inputs with the value 4 is reduced from 5 to 4. This is possible because all the "four" outputs, which trigger circuit 5, never have high potential simultaneously. The next triggering gap is used in circuit 4. The dual full adder 1 processes the value 1, and the dual full adder 2 processes the value 2. <IMAGE>
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申请人 |
MERKLE, PAUL, 7032 SINDELFINGEN, DE |
发明人 |
MERKLE, PAUL, 7032 SINDELFINGEN, DE |