| 摘要 |
The method of testing a memory array of SRAM cells each of which includes memory transistors, bit and bit# lines, precharge circuitry, and an output test terminal involving the steps of connecting selected bit and bit# lines of selected SRAM cells to the output test terminal, disconnecting the memory transistors of the selected SRAM cells from the bit and bit# lines, disconnecting the bit and bit# lines from the precharge circuitry, enabling the column select circuitry to select the columns of the selected SRAM cells, applying a preselected level voltage to the output test terminal, and measuring any current which flows.
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