| 摘要 |
The bus of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. In a first embodiment, a high speed clock signal and slower speed clock enable signal are globally distributed from a central arbiter to agents coupled to the bus. A sending agent utilizes the high speed clock signal for source synchronized data transfers by forwarding the high speed clock signal, along with the data, to one or more receiving agents. Thus, the globally distributed clock signal is used to accomplish source synchronized data transfers. Arbitration requests, by contrast, are processed at the slower clock enable signal rate in a globally synchronous fashion. In addition, by communicating data cycles information from the central arbiter to the receiving agent at the slower clock enable signal rate, the present invention avoids resynchronization and the possibility of metastability. Dead time between packets of data is minimized in the present invention by placing the central arbiter in the center of the bus. An alternative embodiment is disclosed wherein a slower speed clock signal is globally distributed to a plurality of agents and a central arbiter. Each agent then generates a high speed clock signal that is divided down and phase locked to the slower speed clock signal, and this high speed clock signal is then utilized for high-speed, source synchronized data transfers. Arbitration and consistency information are handled at the slower speed clock signal rate. In the alternative embodiment, resynchronization is avoided through the use of a header signal.
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