| 摘要 |
PURPOSE: A multiplier of an equalizer is provided to reduce the electricity consumption amount through the prevention of transitions that are caused by the delay of internal operation signals by arranging a multiple number of bit's input signals, which are inputted into a digital VSB reception system's equalizer, and a multiple number of CSAs(Carry Save Adder), which output a multiple number of sums and round-up numbers that are added in accordance to each bit, as a tree structure. CONSTITUTION: A multiple number of coefficients(70¯75) execute booth encoding and a multiple number of PPGs(Partial Product Generation)(80¯85) controls and operates un-encoded dins with the booth encoders' output signals. A multiple number of CSAs(100¯106) prevents the transitions between the internal operation signals that are caused by the delay by arranging the signals as a tree structure and outputting a multiple number of round-up numbers and a multiple number of sums that have added the various bits' input signals in accordance to the bit classification.
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