| 摘要 |
PURPOSE: A row decoding circuit comprised in a flash memory device is provided to reduce an area occupying in the flash memory device and then to realize a high density. CONSTITUTION: A memory device includes a plurality of sectors, a plurality of global word lines, a global word line selection circuit(100,120) and the first and second local decoders(140). The sectors are connected with local word lines. The global word line selection circuit has the first global decoder(120) for selecting a word line of odd global word lines and the second global decoder(100) for selecting a word line of even global word lines. The first local decoders correspond to the odd global word lines. The second local decoders correspond to the even global word lines. Each of the first and second local decoders has a plurality of drivers connected with the local word lines. Each driver a pull-up transistor connecting a local word line corresponding to a signal of a global word line with a row partial decoder(160), and a pull-down transistor a local word line to a block decoder(180) in response to a signal of a global word line.
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