| 摘要 |
A small-sized and power-saving matched filter circuit is provided. A succeeding stage of a matched filter includes a group of n hold circuits (H21, H22,..., H2n) to which the output signals (Dout1) from a preceding stage are coupled in parallel. The outputs of the hold circuits (H21 - H2n) are connected to multiplier circuits (M2l, M22, ..., M2n), respectively. The multiplier circuits multiply the outputs from the hold circuits (H21 - H2m) by multipliers (d21, d22,..., d2m). The outputs from the multiplier circuits (M21 - M2n) are supplied to a summing circuit (ADD2) to provide the sum (Dout2) (correlation output).
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