发明名称
摘要 PURPOSE:To reduce a response time inexpensively with simple constitution without using a DA converter by providing a control circuit comparing levels of signals fed respectively to two circuits and controlling the level of the signal fed to the circuits. CONSTITUTION:A control circuit 40 receives a control signal SA of a voltage controlled oscillator(VCO) 1 included in a 1st phase locked loop(PLL) and a control signal SB of a VCO 2 included in a 2nd PLL. The control circuit 40 has a function comparing levels of both the control signals and supplying a level signal in response to the signal SA from the VCO 1 to an input terminal of the VCO 6 for a period when the level difference between the signals SA and SB is a set voltage or over. Thus, an expensive DA converter is not required and if the shift in an output frequency f2 is large, the control voltage of the VCO 1 with a fast response is used to apply pre-tuning to the VCO 6 thereby moving the operating state forcibly into the vicinity of the designated frequency. Thus, the whole circuit can attain fast speed response.
申请公布号 JPH0724380(B2) 申请公布日期 1995.03.15
申请号 JP19880185071 申请日期 1988.07.25
申请人 发明人
分类号 H03L7/22;H03L7/187 主分类号 H03L7/22
代理机构 代理人
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