发明名称 DEVICE AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a device and a method for designing a semiconductor integrated circuit which can replace a normal cell with a low power consumption cell in consideration of the margin of a cell arrangement area. SOLUTION: In the device 1 for designing the semiconductor integrated circuit, a replacement cell candidate selection part 13 selects low power consumption cells as replacement cell candidates with respect to a normal cell extracted by a replacement object cell extraction part 12 as an object to be replaced with a low power consumption cell based on the analytic result of a timing analyzing part 11 to a netlist 200 designed in the normal cell, and a power consumption reduction effect analyzing part 14 ranks the low power consumption cells as replacement candidates in the order of the larger reduction quantity of power consumption due to replacement, and a replacement execution cell determination part 15 adds the increase quantity of a cell arrangement area in the order of the higher rank, and determines the low power consumption cell of a rank until it reaches cell arrangement area increase permissible quantity 140 as a replacement execution cell, and a cell replacement execution part 16 executes cell replacement based on the determination, and outputs a post-replacement netlist 300. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007323203(A) 申请公布日期 2007.12.13
申请号 JP20060150564 申请日期 2006.05.30
申请人 TOSHIBA CORP 发明人 KAWABE NAOYUKI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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