发明名称 HIGH WITHSTANDING-VOLTAGE PLANAR TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To prevent the lowering of withstanding voltage between a base and a collector at low currents by surrounding other residual base regions through a high-resistance isolation layer by one base region of a plurality of base regions while forming a guard ring layer on the outside of one base region through the high-resistance isolation layer. CONSTITUTION:An N-type impurity is diffused selectively to an N-type substrate to shape a collector layer 1, a base region 2 in a pre-step transistor A is surrounded insularly by a base region 3 in a post-step transistor B through a high-resistance isolation layer 10, and a P-type impurity is diffused selectively so as to form guard ring layers 4, 5, 6 around these regions. An N-type impurity is diffused selectively to the base regions 2, 3 and the outside of the guard ring layer 6, thus forming emitter regions 7, 8 and a channel stopper region 9. Accordingly, when bias voltage is applied between the base 2 and a collector 1 in the pre-step transistor A, there is no concentration section of an electric field, and withstanding voltage between the base and the collector is kept constant regardless of the magnitude of currents.
申请公布号 JPS61206262(A) 申请公布日期 1986.09.12
申请号 JP19850046468 申请日期 1985.03.11
申请人 SHINDENGEN ELECTRIC MFG CO LTD 发明人 TANAKA MITSUGI;ICHIKAWA KATSUNORI
分类号 H01L29/73;H01L21/331;H01L29/06;H01L29/732 主分类号 H01L29/73
代理机构 代理人
主权项
地址