| 摘要 |
<p>PURPOSE:To decrease the number of delay correcting circuits and to perform accurate phase comparison by simple constitution by inputting a clock signal and a signal whose timing is precessed with a read signal to a 2nd FF and a delay circuit, and comparing the phases of the outputs of them with each other. CONSTITUTION:The output of a D type FF circuit is determined unequivacally by a level inputted to an input terminal D at the time of the arrival of a clock pulse and an input before pulses arrive at the clock terminals of FF circuits 10 and 20 are outputted after the arrival to cause one-clock delay. An output signal (9) obtained by extracting a clock RCK signal 3 at the timing of an R1phi signal (2) by the circuit 10 becomes a timing signal in phase with the signal (2). The W1phi signal (1) and the signal (9) inputted to the circuit 20 are based upon timing pulses when the memory cells of the 1st stage in a buffer memory are read as data. Further, timing pulses at the time of writing to memory cells are used as a clock for timing at the same time and the phases are compared, so any delay circuit is required.</p> |
