发明名称 Pattern examination method for IC chips
摘要 The method generates an image of a sample. A pattern on the sample is examined. The method involves inputting a reference image which corresponds to an image of the sample, into a memory. The reference image read out from the memory is compared withe the image of the sample. Differences between the reference image and the sample image are identified as defects. The method further determines the probability that the sample in its final form has a fatal defect, on the basis of the identified different sections. The method may also involve classifying the difference sections into different defects e.g. short circuit, open circuit, fine holes.
申请公布号 DE19803021(A1) 申请公布日期 1998.07.30
申请号 DE1998103021 申请日期 1998.01.27
申请人 HITACHI, LTD., TOKIO/TOKYO, JP 发明人 MIZUNO, FUMIO, TOKOROZAWA, SAITAMA, JP
分类号 G01B11/24;G01B15/04;G01N21/88;G01N23/225;G06T1/00;G06T7/00;H01L21/66;(IPC1-7):G06K9/00;G01B11/00;G01B11/03;G01N23/22 主分类号 G01B11/24
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