SYNCHRONOUS MEMORY DEVICE HAVING DATA INPUT/OUTPUT CONTROL CIRCUIT

摘要

PURPOSE: A synchronous memory equipped with a data input/output control circuit is provided to internally synchronize to an external clock according to changeable burst length and burst mode by controlling a data input/output buffer circuit. CONSTITUTION: A data input/output control circuit(100) is composed of the second pulse generation section(170) and the first driving section(180) for controlling the control circuit(100), and the third pulse generation section(190) and the second driving section(200) for controlling a data input buffer(120). The second pulse generation section(170) receives a read activation signal and a pulse signal. The first driving section(180) generates a driving signal for driving a data output buffer(110). The third pulse generation section(190) reads a write activation signal. The second driving section(200) outputs a driving signal for driving a data input buffer(120).