| 摘要 |
PURPOSE: A cache capable of a memory is provided to maximize an application of a cache by adding least control circuit to an n-way cache structure, and by using the cache as a main memory. CONSTITUTION: A tag register(64) of a way 0(60) is set as '0'. A tag register(65) of a way 1(61) is set as '1'. A tag register(66) of a way 2(62) is set '2'. A tag register(67) of a way 3(63) is set as '3'. Valid bit registers(68,69,70,71) of each way are respectively set as '1'. A 4-way cache memory is operated as a main memory. If a mapping address start point is changed into another address instead of 0 address, tag registers values are appropriately set.
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