发明名称 |
CLOCK SYNCHRONIZATION DEVICE AND METHOD USING DUAL PHASE CONTROL IN DIGITAL CLOCK SYNCHRONOUS SYSTEM |
摘要 |
PURPOSE: A clock synchronization device and method using a dual phase control is provided to carry out the control by a phase error data and the control by a load data of a counter at once as to improve an accuracy of a phase error data. CONSTITUTION: A clock synchronization device in a digital clock synchronous system includes a digital/analog converter(107) and a voltage controlled oscillator(109). In the clock synchronization device using a dual phase control, a dual phase detection circuit(115) receives a reference clock, a loop clock and a system clock to output a phase error data and a load data. A dual port RAM(103) receives the phase error data and the load data to store the received data sequently. A controller(105) reads the phase error data and the load data with a described period to double-control the voltage controlled oscillator through the digital converter.
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申请公布号 |
KR20010008838(A) |
申请公布日期 |
2001.02.05 |
申请号 |
KR19990026867 |
申请日期 |
1999.07.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, BEOM SU |
分类号 |
H03L7/087;(IPC1-7):H03L7/087 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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