Frequency scaling method, circuit and associated all-digital phase-locked loop

摘要

A frequency scaling method is disclosed. The method is used for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency. The method includes: stopping a feeding of a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO in order to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce the phase detecting result according to the second frequency. An associated ADPLL and a frequency scaling circuit are also disclosed.

主权项

1. A frequency scaling method for changing an output frequency of an all-digital phase-locked loop (ADPLL) from a first frequency to a second frequency different from the first frequency, the method comprising:
stopping feeding a first oscillator tuning word (OTW) to a digitally controlled oscillator (DCO) of the ADPLL, wherein the first OTW is generated based on a phase detecting result obtained with respect to the first frequency; feeding a second OTW to the DCO to change the output frequency from the first frequency to the second frequency; and performing a zero phase restart (ZPR) operation to produce a phase detecting result according to the second frequency.