发明名称 |
Method and circuit for increased noise immunity for clocking signals in high speed digital systems |
摘要 |
Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
|
申请公布号 |
US7034566(B2) |
申请公布日期 |
2006.04.25 |
申请号 |
US20040777952 |
申请日期 |
2004.02.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CRANFORD, JR. HAYDEN C.;STEVENS JOSEPH M. |
分类号 |
H03K17/16;H03K19/00;H03K19/003;H03K19/0185 |
主分类号 |
H03K17/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|