| 摘要 |
Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I-) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q-) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.
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