| 摘要 |
A full adder composed essentially of six identical logic circuits each arranged to receive inputs A1, A2 . . . B1, B2... and to produce outputs C = A1 + A2... + B1 + B2... and C = A1 + A2... (B1 + B2...), the logic circuits being arranged to receive addend input values Xi and Yi and carry inputs Zi-1, and their complements, and being arranged in at least two groups of circuits, the first group producing an output carry signal and the second group receiving inputs from the first group and producing an output sum signal.
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