发明名称 RECEIVING CIRCUIT OF DIAL PULSE
摘要 PURPOSE:To enhance flexibility of a receiving logical function by storing various types of status information necessary for a receiving action of a dial pulse in plural addresses as dispersed and by executing renewal logical processing of various types of status information. CONSTITUTION:A dial pulse receiving circuit has a status information holding memory MEM and a general-purpose logical operation circuit group GLG. The general-purpose logical operation circuit group GLG has various general-purpose logical operation circuits such as an adder ADD required when reception processing of a dial pulse is carried out, a gate GA to carry out exclusive OR processing, gates GB and GC to execute AND processing and a gate GD to execute OR processing; a registor REG to accumulate various types of status information read-out from each address of the status information holding memory MEM, gate groups GG1 and GG2 to transmit various types of status information accumulated in the registor REG and to transmit an output of a logical operation circuit to the memory MEM or buffer registors BR1-BR3, and a control holding memory CM.
申请公布号 JPS60136495(A) 申请公布日期 1985.07.19
申请号 JP19830249890 申请日期 1983.12.24
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 KITAMURA NOBUAKI;KOGURE KOUJI
分类号 H04Q1/32;(IPC1-7):H04Q1/32 主分类号 H04Q1/32
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