| 摘要 |
PURPOSE:To check generation of deterioration of the gate withstand voltage or the FET characteristic during the manufacturing process of a field effect transistor by a method wherein a gate metal layer is adhered after heat treatment of a contact metal layer, and moreover after the contact metal layer is patterned to form a source and a drain, a recess part is formed by etching. CONSTITUTION:An undoped GaAs layer 2 as a buffer layer, and an N type GaAs layer 2 as an active layer are adhered in order on a semiinsulating substrate 1. A positive resist 6 is adhered wholly thereon, and patterning is performed to leave a recess forming region. Then an AuGe/Au layer is adhered on the whole surface of the substrate as a contact metal layer 4 to form a source and a drain. The positive resist 6 and the contact metal layer 4 on the recess forming region is lifted off to form the source and the drain. Then a silicon dioxide layer is adhered as an insulating layer 7, and heat treatment of the contact metal layer 4 is performed. The insulating layer 7 is etched only in the vertical direction to the substrate, and the insulating layers 7 are left only at the step difference parts coming in contact with the side walls of the contact metal layers 4. Then a recess is formed using the insulating layers 7 as masks. |
