System employing negative feedback for decreasing the response time of a memory cell.

摘要

First and second lines respectively receive first and second complementary input signals representing a binary bit. Each of the input signals has first and second logic levels respectively corresponding to a binary "1" and a binary "0". The input signals produce a current through a load in accordance with the relative logic levels of the first and second input signals. The difference between the logic levels of the input signals is amplified and introduced as a negative feedback to a particular one of the first and second lines in accordance with the relative logic levels of the signals on the lines. The feedback causes a current to be produced in the load with a polarity opposite to the polarity of the current produced in the load by the input signals and with a magnitude less than the magnitude of the current produced in the load by the input signals. The negative feedback is effective in minimizing the time for the load to respond to changes in the relative logic levels of the first and second input signals. In this way, the frequency of response to a system including the circuitry of this invention can be significantly increased. The embodiment described above may be used in a system in which first particular input signals are provided to identify a selected word and second particular input signals are provided to identify a bit in the word one and in which a cell (a load) is selected common to the selected word and the selected bit. The circuitry described above may be included to minimize the time for producing in the load a signal representative of the selection of such cell.