| 摘要 |
<p>PURPOSE:To shorten a delay time and to set up the delay time to the same value as the case using a simple substance for a CPU core part by activating the output of the 1st latch circuit prior to the rise of a clock. CONSTITUTION:Since a condition signal CND is activated faster than a clock phiA, an address value is outputted faster from the 1st latch circuit 11 in a CPU core part by using the condition signal CND as the clock input of the 1st latch circuit 11. Since the value can arrive at the input of the 2nd latch circuit 16 for outputting addresses before the clock phiA is activated, the address value can be transmitted from the 2nd latch circuit 16 to an output terminal through an address output buffer 13 simultaneously with the activation of the clock phiA. Thereby, the delay time between the clock input and the address output is allowed to coincide with that of the case using a simple substance for the CPU core part.</p> |
