发明名称 |
Multiplier having a reduced number of partial product calculations |
摘要 |
An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.
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申请公布号 |
US5119325(A) |
申请公布日期 |
1992.06.02 |
申请号 |
US19900622029 |
申请日期 |
1990.12.04 |
申请人 |
MOTOROLA, INC. |
发明人 |
VIOT, J. GREG;BROSEGHINI, JAMES L.;HARTUNG, EYTAN;DUNN, JOHN P. |
分类号 |
G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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